As the interconnect system in the back-end of integrated circuit chips shrinks, going from one technology node to the next, the line-to-line spacing between conductive lines also continues to shrink. As such, the dielectric thickness between the lines has presently reached values on the order ranging from about 35 nm to about 90 nm. Due to the desire to lower the line-to-line capacitance to minimize the RC time response of the interconnect network, low-k dielectric materials have been introduced as inter-metal-dielectrics (IMD). However, these new insulators no longer have the dielectric-strength of pure dense amorphous silicon oxides. In most low-k dielectric materials, their lower density and the presence of weaker bonds (such as Si—C bonds) introduce charge traps, and can potentially host mobile ions. These mobile ions can aid early breakdown events under electrical stress.
In addition, the necessity for the integration of additional dielectrics films as etch-stop layers, and diffusion barriers on top of the copper metal lines, gives rise to interfaces that span between the lines and open new channels for early breakdown. Because the profile of the etched trenches is often adjusted for copper filling optimization, in the damascene process presently used by most of the integrated circuit industry, the line-to-line spacing becomes even narrower at the top of the lines. This gives rise to the occurrence of the higher electric field near the interface between the low-k dielectric material and the diffusion-barrier/etch-stop layer above it.
Near the end of the fabrication of the microelectronic device, a dielectric test is conducted to determine both the quality and reliability of the dielectric. Usually, this test involves determining the electrical breakdown field of the dielectric within test devices. The most commonly used model to predict the time to breakdown (tbd) for silica-based dielectrics under an electric field E, states that:tbd=A·e((ΔHγE)/(kbT)) 
where A is a constant, ΔH is the zero-field activation energy, γ is the field-acceleration parameter (which may be associated with the Si—O bond dipole moment that interacts with the electric field to lower the bond strength), kb is the Boltzmann constant, and T is the temperature in Kelvin.
For a given temperature T, γ(T) typically can be extracted from a series of time dependent dielectric breakdown (TDDB) tests. A collection of devices under test (DUTs: capacitors, comb-comb or comb-serpent test structures), which are chosen to be uniformly distributed across the wafer, are stressed at a constant voltage and the time-to-breakdown distributions are recorded. By virtue of area scalability, these distributions preferably obey Weibull statistics, for example. From the characteristic time-to-breakdown tbd(E), under various electric fields E, one can obtain the value of γ, and extrapolate the dielectric lifetime to operating voltage at any required confidence level.
Because TDDB tests are slow, often one cannot test a sufficient number of DUTs to obtain good enough statistics. FIGS. 1A and 1B show two conventional TDDB test patterns that a test structure may include. FIG. 1A shows a comb-comb test pattern 21. FIG. 1B shows a comb-serpent test pattern 22. Using either of the test patterns (21 or 22) of FIGS. 1A and 1B, the time to dielectric breakdown under a constant voltage can be determined. But when the dielectric breaks down using these conventional test patterns (FIGS. 1A and 1B), there is usually a serious burn-out that damages a relatively large area at and surrounding the point of initial failure. Although the time to dielectric breakdown can be measured accurately, the failure mode add characteristics of the failure is usually unobservable due to the large damage area. A need exists for a way to measure the time to failure while also providing a way to observe the failure mode and failure characteristics.